1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming fins for FinFET semiconductor devices and the selective removal of some of the fins.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a traditional FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate cap 20. The fins 14 are formed by etching a plurality of trenches 13 into the substrate 12. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height 14H, a width 14W and an axial length 14L. The axial length 14L corresponds to the direction of current travel, i.e., the gate length (GL) of the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 is the channel region of the FinFET device 10. In a conventional process flow, the portions of the fins 14 that are positioned outside of the spacers 18, i.e., in the source/drain regions of the device 10, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes to form additional semiconductor material on the portions of the fins 14 in the source/drain region.
Both planar transistor devices and FinFET transistor devices have an isolation structure, e.g., a shallow trench isolation structure that is formed in the semiconducting substrate around the device so as to electrically isolate the transistor device. Traditionally, isolation structures were always the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures into the substrate and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the transistor devices. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching additional trenches into the substrate to thereby define the fins. As FinFET devices have been scaled (i.e., reduced in physical size) to meet ever increasing performance and size requirements, the width 14W of the fins 14 has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm. As the dimensions of the fins 14 became smaller, problems arose with manufacturing the isolation structures before the fins 14 were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate.
Various techniques have been employed to try to overcome the above-mentioned problems. One manufacturing technique involves initially forming trenches 13 in the substrate 12 to define multiple “fins” that extend across the substrate 12, and thereafter removing some of the fins 14 (or portions thereof) where larger isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 14 to very small dimensions due to the more uniform etching environment in which the etching process that forms the trenches 13 is performed.
As indicated above, after the trenches 13 are formed, some portion of the fins 14 must be removed to create room for or define the spaces where isolation regions will ultimately be formed. There are two commonly employed techniques for accomplishing the goal of removing the desired number and portions of the fins 14. One such removal process is typically referred to as “Fins-cut-First,” as will be described with reference to FIGS. 1B-1E. FIG. 1B depicts the device 10 after a patterned hard mask layer 30, e.g., comprised of a patterned layer of silicon nitride (pad-nitride) and a patterned layer of silicon dioxide (pad-oxide) was formed above the substrate 12 in accordance with the desired fin pattern and pitch. In the depicted example, only a single fin will be removed, i.e., the fin 14 corresponding to the feature 30A, to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed. Of course, the entire axial length 14L of the fin 14 need not be removed, but it may be in some applications.
FIG. 1C depicts the device 10 after a patterned masking layer 34, e.g., a patterned layer of photoresist, was formed above the patterned hard mask layer 30. The patterned masking layer 34 has an opening 34A that exposes the feature 30A for removal.
FIG. 1D depicts the device 10 after an etching process was performed through the patterned masking layer 34 so as to remove the exposed feature 30A of the patterned hard mask layer 30.
FIG. 1E depicts the device 10 after the patterned masking layer 34 was removed and after an etching process was performed through the patterned hard mask layer 30 (without the feature 30A) so as to define full-depth trenches 13 in the substrate 12 that define the fins 14. Due to the removal of the feature 30A, this etching process removes the portions of the substrate 12 that would have otherwise formed a fin 14 in the area under the feature 30A. One problem with the “fins-cut-first” approach is that it inevitably causes different fin sizes, i.e., the dimensions 14X and 14Y are different. This is especially true between fins 14 inside an array of fins and the fins at the edge of the active region that is close to the isolation region. These dimensional variations occur due to etch loading effects wherein there are different etch rates and etch profiles due to differing patterning densities, pitch, etc. Another problem with the “fins-cut-first” approach is with potential misalignment of the opening 34A in the masking layer 34 (See FIG. 1C). If the opening 34A is perfectly aligned (as depicted in FIG. 1C) then only the feature 30A will be removed from the patterned hard mask layer 34. However, if the opening 34A is misaligned, as depicted by the dashed line opening 34X that shifted to the right, then portions of both the features 30A and 30B will be etched, thereby resulting in incomplete removal of the fin corresponding to the feature 30A (the fin that is desired to be removed) and partial removal of the fin corresponding to the feature 30B (a fin that was not intended to be removed).
FIG. 1F depicts the device 10 after several process operations were performed. First, a layer of insulating material 36, such as silicon dioxide, was formed so as to overfill the trenches 13. A chemical mechanical polishing (CMP) process was then performed to planarize the upper surface of the insulating material 36 with the top of the patterned hard mask 30. Thereafter, an etch-back process was performed to recess the layer of insulating material 36 between the fins 14 and thereby expose the upper portions of the fins 14, which corresponds to the final fin height of the fins 14. At this point in the process, the patterned hard mask 30 may or may not be thereafter removed. Next, the gate structure (not shown) of the device 10 may be formed using either gate-first or gate-last manufacturing techniques.
One technique that has been employed to create the initial patterned hard mask 30 is generally known as “sidewall image transfer” (SIT). In the SIT technique, patterned mandrel features are formed above the substrate, and sidewall spacers are then formed adjacent patterned mandrel features. Thereafter, the mandrel features are removed leaving the sidewall spacers which constitute the pattern for the hard mask layer. The SIT process can be performed as a single patterning process (for fin pitches of about 40 nm or greater) or essentially repeated using a so-called memorization layer to repeat the process for fins having a pitch less than 40 nm, e.g., less than 32 nm. In this latter process, the process would involve forming a first set of spacers against a first group of mandrel features, removing the first group of mandrel features, transferring the pattern of the first set of spacers to an underlying memorization layer, removing the first set of spacers, forming a second set of spacers adjacent the features of the patterned memorization layer, which are treated as a second group of mandrel features, removing the second group of mandrel features so as to define a second group of spacers that corresponds to the desired fin pattern and desired fin pitch of the fins, and etching the fins into the substrate using the fin pattern defined by the second group of spacers. Whether single or double SIT techniques are involved, the net result is the formation of a single layer of spacers that correspond to the fin pattern and fin pitch of the fins to be formed in the substrate.
The present disclosure is directed to various methods of forming fins for FinFET semiconductor devices and the selective removal of some of the fins that may solve or reduce one or more of the problems identified above.